1. Field of the Invention
The present invention relates to formation of a contact using a self-alignment scheme and, more particularly, to a method of manufacturing a semiconductor device such as a DRAM whose yield can be improved by a small number of manufacturing steps.
2. Description of the Related Art
In conventional steps in manufacturing a semiconductor device, for example, when a structure, having a lower wiring layer and an upper wiring layer, which is electrically connected to a conductive region of the surface of a semiconductor substrate through a contact is to be formed, as shown in FIG. 17, a gate insulating film 2 consisting of an oxide film is formed on one major surface of a semiconductor substrate 1 having a conductive region 1a formed on the surface of the semiconductor substrate 1, a conductive material layer consisting of polysilicon is stacked on the entire surface of the semiconductor substrate including the gate insulating film 2, and a silicon oxide film 4 is formed on the result structure to have a predetermined thickness. A resist pattern having a shape of wirings to be formed is patterned, the resultant structure is anisotropically etched by using the resist pattern as an etching mask, and conductive material layers prospectively serving as the silicon oxide film 4 and wirings 3 are sequentially etched to have predetermined sizes, respectively. Thereafter, an insulating film consisting of a silicon oxide film having a uniform thickness is formed on the entire surface of the semiconductor substrate 1 by a CVD technique. Thereafter, the resultant structure is etched back until one major surface of the semiconductor substrate 1 is partially exposed, thereby forming side walls 5 on the side surfaces of the wirings 3, the silicon oxide films 4, and the gate insulating films 2. The silicon oxide film 4 and the side walls 5 which are in contact with the upper and side surfaces of each wiring 3 are formed as protective films. A silicon oxide film serving as an insulating interlayer 6 is formed on the entire surface of the semiconductor substrate 1, and a resist pattern 7 having an opening having the same shape as that of a contact hole is formed on the insulating interlayer 6.
Thereafter, as shown in FIG. 18, the resultant structure is anisotropically etched until one major surface of the semiconductor substrate 1 is partially exposed by using the resist pattern 7 as an etching mask, thereby forming a contact hole 8 in the insulating interlayer 6. The resist pattern 7 is removed, and a conductive material is buried in the contact hole 8, thereby forming a contact 9 shown in FIG. 19. Thereafter, an upper wiring layer 10 or the like is formed on the contact 9. In this manner the upper wiring layer 10 is electrically connected to the conductive region 1a is formed on the surface of the semiconductor substrate 1 through the contact 9.
However, when the contact 9 is to be formed between two wirings 3, the resist pattern 7 serving as the etching mask is positionally shifted. When the distance between the two wirings 3 is shorter than the diameter of the contact hole 8, as shown in FIG. 18, in anisotropic etching for forming the contact hole 8, the silicon oxide films 4 formed as the protective films of the wirings 3 and the side walls 5 constituted by a silicon oxide film are simultaneously etched at a selectivity ratio which is almost equal to that of the insulating interlayer 6, and the wirings 3 are exposed in the contact hole 8. When the wirings 3 are exposed when the contact hole 8 is formed, the contact 9 is formed by burying a conductive material in the contact hole 8 in the next step. For this reason, the wirings 3 may be short-circuited to the contact 9.
In order to suppress the short circuit between the wirings 3 and the contact 9 described above, in another conventional method of manufacturing a semiconductor device, as shown in FIG. 20, the silicon oxide films 4 and the side walls 5 serving as the protective films of the wirings 3 are formed. Thereafter, an etching stopper film 11 constituted by a silicon nitride film is stacked, and the etching stopper film 11 can be anisotropically etched at a high selectivity ratio when the contact hole 8 is formed. In still another conventional method of manufacturing a semiconductor device, as shown in FIG. 21, before the resist pattern 7 serving as an etching mask is formed, a reflection prevention film 12 is formed on the surface of the insulating interlayer 6. For this reason, the resist pattern 7 can be formed at high dimensional precision. In this case, removal of the reflection prevention film 12 and removal of the etching stopper film 11 on a contact formation region are performed in different steps, respectively.
As described above, in a conventional method of manufacturing a semiconductor device, when a contact is formed in a self-alignment manner between two adjacent wirings, as shown in FIG. 19, the wirings 3 and the contact 9 are short-circuited or almost short-circuited by shifting of a contact formation position caused by shifting of a contact formation position. The contact 9 and the wirings 3 are electrically influenced to each other. In addition, in another conventional method of manufacturing a semiconductor which solves the problem, when the etching stopper film 11 and the reflection prevention film 12 are formed to strengthen protection of the wirings 3 and to improve the dimensional precision of the etching mask, the etching stopper film 11 and the reflection prevention film 12 are removed in different steps, respectively. For this reason, the number of steps increases to remove these films, and a yield disadvantageously decreases.